Design Compiler is the industry-standard RTL synthesis solution. It transforms Register Transfer Level (RTL) code (Verilog or VHDL) into an optimized gate-level netlist by mapping the design to a specific . Key 2021+ Features:
report_area -hierarchy > $report_dir/area.rpt report_power -analysis_effort high > $report_dir/power.rpt synopsys design compiler tutorial 2021
# Save the synthesized design write -format ddc -hierarchy -output outputs/final.ddc $report_dir/area.rpt report_power -analysis_effort high >
You can use read_verilog or the modern analyze and elaborate flow. The latter is preferred as it allows for better error checking and parameter passing. synopsys design compiler tutorial 2021
These are physical rules dictated by the foundry technology library.